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Objective : Evaluate measurement tecniques to realize a routine library for parallel test (HP BASIC or C++) on HP4062 and Keithley S600, analyze the interaction between the layout and the test structure to be used for parallel test.Apply for position
The wafer level reliability (WLR) laboratory performs accelerated reliability tests of semiconductor devices as part of the technological qualification of a product. Furthermore, the laboratory performs periodical tests as monitor of the production line to reduce the probability that deviant material arrives to the final customer.
There are three main portions of the technology process that are evaluated by WLR tests:
* Device reliability is assessed by Hot Carrier Injection (HCI) and Bias Temperature Instability (BTI) tests
* Gate Oxide Integrity is assessed by Time Dependent Dielectric Breakdown (TDDB) and Voltage ramp (V-ramp) tests
* Metal Interconnects are assessed by Electromigration (EM), Stress Migration (SM), and Inter Layer Dielectric (ILD) TDDB
The execution of accelerated reliability testing requires a large amount of electrical measurements to monitor over time the characteristics of the various devices under stress. For this purpose are used machines and tools (Prober and Testers) that allows to perform electrical measurements automatically.Apply for position
The Device Modeling Engineer develops the models for the simulation of the device behavior that allow the analog and/or digital designer to verify the functionality of his circuit under different conditions. The main activities of the device modeling engineer are the definition of test structures, the preparation of measurement instructions, the analysis, interpretation and processing of measurement data and the extraction of model parameters and subsequent implementation to the appropriate model structure. The final model has to be prepared fitting the PDK (process design kit) and it has to include all required and available parameters (e.g. Monte Carlo, Mismatch, Noise, Corners, etc…).
A high level of quality awareness during the comparison of measurement data versus simulation results and a frequent verification of the actual values in the context of the device specification and EDR (electric design rules) are strongly required. Furthermore the daily business includes the communication and interaction with the process and technology departments, the PDK team and the technical support for customers and IP partners.Apply for position
The TCAD Engineer applies advanced process & device modeling tools during process development for insights into scaling, optimization and feasibility studies as applicable. Works closely with Process Integration engineers to design experiments based on modeling and/or existing experimental results. Interacts with a variety of teams including process integration, characterization, circuit design, reliability and product engineers to analyze and debug device and circuit-related issues during process development.Apply for position
Study on analytical recovery capability for metal elements from silicon wafer surface by VPD/ICP-MS
The PDK Development Engineer is responsible to develop, build and maintain the Process Design Kit’s (PDK) containing all needed information related to a process or technology, converted into a design framework, that allow a customer to design their products based on the technology offered by the fab. The PDK Development Engineer develops the PDK based on the information coming from several groups like technology, device development, TCAD, DR-Team, Test-team, etcApply for position
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