Work in LFoundry

  1. Contribute

    Join the LFoundry team and contribute to the innovative solutions that bring our customers’ ideas to life.

  2. Challenge

    You can help LFoundry to shape innovation on a global scale by working to make our customers’ visions a reality, no matter how big the challenge is.

  3. Transforming

    Work with us and become an essential player, transforming innovation into reality.

STAGE - Communication, Corporate Values Deployment & Employer Branding

  • Working area: Human Resources & General Affairs
  • Facility: Avezzano (Italy)
  • Job time: Stage

1. Design and execute a Communication and Training plan on Corporate values ​​in order to create a corporate culture in line with SMIC (headquarter)

2. Execution of communication&deployment plan related to the EVP (Employee Value Proposition) of LFoundry in order to communicate the set of policies, processes and programs (benefits) provided by the company to the employees

3. Manage communication tools for trade shows in Europe / Asia

5. Manage internal communication tools: newsletters, company intranet, business TV, mailings, contests, events.

6. Design climate survey to monitor employees' engagment

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Thesis - Implementation and evaluation of structures and tecniques for parametric measurement in parallel

  • Facility: Avezzano (Italy)
  • Job time: Thesis

Objective :  Evaluate measurement tecniques to realize a routine library for parallel test (HP BASIC or C++) on HP4062 and Keithley S600, analyze the interaction between the layout and the test structure to be used for parallel test.

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Thesis

  • Working area: Thesis Title: Development of an automatic measurement system for the execution of Reliability Tests on semiconductor devices
  • Facility: Avezzano (Italy)
  • Job time: Thesis

The wafer level reliability (WLR) laboratory performs accelerated reliability tests of semiconductor devices as part of the technological qualification of a product. Furthermore, the laboratory performs periodical tests as monitor of the production line to reduce the probability that deviant material arrives to the final customer.

There are three main portions of the technology process that are evaluated by WLR tests:

* Device reliability is assessed by Hot Carrier Injection (HCI) and Bias Temperature Instability (BTI) tests

* Gate Oxide Integrity is assessed by Time Dependent Dielectric Breakdown (TDDB) and Voltage ramp (V-ramp) tests

* Metal Interconnects are assessed by Electromigration (EM), Stress Migration (SM), and Inter Layer Dielectric (ILD) TDDB

The execution of accelerated reliability testing requires a large amount of electrical measurements to monitor over time the characteristics of the various devices under stress. For this purpose are used machines and tools (Prober and Testers) that allows to perform electrical measurements automatically.

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DEVICE MODELING ENGINEER

  • Facility: Landshut (Germany)
  • Job time: Full Time

The Device Modeling Engineer develops the models for the simulation of the device behavior that allow the analog and/or digital designer to verify the functionality of his circuit under different conditions. The main activities of the device modeling engineer are the definition of test structures, the preparation of measurement instructions, the analysis, interpretation and processing of measurement data and the extraction of model parameters and subsequent implementation to the appropriate model structure. The final model has to be prepared fitting the PDK (process design kit) and it has to include all required and available parameters (e.g. Monte Carlo, Mismatch, Noise, Corners, etc…).

A high level of quality awareness during the comparison of measurement data versus simulation results and a frequent verification of the actual values in the context of the device specification and EDR (electric design rules) are strongly required. Furthermore the daily business includes the communication and interaction with the process and technology departments, the PDK team and the technical support for customers and IP partners.

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TCAD Engineer

  • Facility: Avezzano (Italy)
  • Job time: Full Time

The TCAD Engineer applies advanced process & device modeling tools during process development for insights into scaling, optimization and feasibility studies as applicable. Works closely with Process Integration engineers to design experiments based on modeling and/or existing experimental results. Interacts with a variety of teams including process integration, characterization, circuit design, reliability and product engineers to analyze and debug device and circuit-related issues during process development.

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STAGE - Chemical Laboratory

  • Facility: Avezzano (Italy)
  • Job time: Stage

Study on analytical recovery capability for metal elements from silicon wafer surface by VPD/ICP-MS

Optical performances of CMOS imagers can be affected by contamination caused by several elements found, even if in extremely low concentration, in semiconductor production environment. In particular, contamination by noble elements like, for example, Gold or Silver, is extremely critical since these elements have a very low migration rate in the silicon, so they are not easily segregated into the gettering sites. They remain electrically active, and contribute to the so called “hot pixel” defects. Unfortunately, the noble elements are also very difficult to be effectively detected by VPD/ICP-MS, the technique traditionally and successfully used to detect most of the other elements (like Fe, Cr, Ni, Na, Ca...). In fact, the chemical mixtures typically used to dissolve noble metals (like Aqua Regia) are very aggressive to the silicon substrate as well, damaging the wafer surface and making recovery by the automated equipment used for this technique (VPD) very difficult and not reliable. In order to allow the implementation of routine analysis for the full elemental range of interest, alternative chemistries should be defined (through theoretical modeling and analytical test confirmation), capable to assure acceptable analytical recovery for noble elements and the other common elements at same time.

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STAGE - Chemical Laboratory

  • Facility: Avezzano (Italy)
  • Job time: Stage


Characterization of VOC contamination in fab c/r environment, and subsequent set-up of a monitoring methodology and strategy

VOC (Volatile Organic Compounds) may affect semiconductor production yield by defect generation (e.g. in ECP process) or damaging the lens coating of photolithography production equipment. VOC concentration and composition in the fab c/r environment depends on internal and external sources, which may change for seasonal reasons as well. A characterization of the contamination is necessary to establish the most effective methodology and strategy for VOC monitoring.

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PDK Development Engineer

  • Facility: Landshut (Germany)
  • Job time: Full Time

The PDK Development Engineer is responsible to develop, build and maintain the Process Design Kit’s (PDK) containing all needed information related to a process or technology, converted into a design framework, that allow a customer to design their products based on the technology offered by the fab. The PDK Development Engineer develops the PDK based on the information coming from several groups like technology, device development, TCAD, DR-Team, Test-team, etc

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Spontaneous Application

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